1. Technical Field
Various embodiments generally relate to semiconductor packages, and more particularly, to technologies for allowing a same data mask address mapping to be retained even when the design of a package has changed.
2. Related Art
Semiconductor memory devices are continuously being developed to increase their degree of integration and operating speeds. In order to increase an operating speed, a so-called synchronous memory device capable of operating in synchronization with a clock provided from an outside of a memory chip has been used.
An SDR (single data rate) synchronous memory device was first used. The SDR synchronous memory device may input and output one quantity of data through one data pin for one cycle of a clock in synchronization with the rising edge of the clock. The clock may be provided from outside the memory device.
However, the SDR synchronous memory device cannot satisfy the speed of a system requiring high speed operations. Accordingly, a DDR (double data rate) synchronous memory device may be used to process two quantities of data per one cycle of a clock.
In the DDR synchronous memory device, two quantities of data are consecutively inputted and outputted through each data input/output pin, in synchronization with the rising edge and the falling edge of a clock. The clock signal may be inputted from outside the DDR synchronous memory device. Therefore, a bandwidth of at least two times wider than the conventional SDR synchronous memory device may be realized without increasing the frequency of the clock. Thus, a high speed operation may be correspondingly achieved.
Semiconductor devices may be designed to consume less power. Data pattern information signals may be used by being defined as a specification.
In particular, a memory for a high speed operation (for example, the Graphics Double Data Rate version 5 (GDDR5)) capable of receiving addresses at not only the rising edge but also the falling edge of an external clock is being designed. Since it is possible to receive addresses two times per one cycle, the number of address pins may be decreased when compared to a conventional semiconductor memory device. Additionally, an extra number of pins may be connected with a power supply voltage or a ground voltage to increase the operation speed of the semiconductor memory device.
In a semiconductor memory device such as a dynamic random access memory (DRAM), in order to achieve a larger capacity from a unit area, a plurality of semiconductor chips (or dies) are stacked and then packaged.
A semiconductor memory device in which only one semiconductor chip is packaged is referred to as a single die package (SDP). A semiconductor memory device in which two semiconductor chips are stacked and packaged is referred to as a dual die package (DDP). A semiconductor memory device in which four semiconductor chips are stacked and packaged is referred to as a quad die package (QDP).
A semiconductor memory device may have data mask pins for receiving data mask information or may receive data mask information through address pins, according to a specification inherent to each device.
In the case of a dual die package (DDP) in which two dies are packaged together, data mask mapping is differentiated when compared to a single die package (SDP).
In other words, in the dual die package, the two dies share address command pins, but memory core regions of the respective dies operate independently.